Comparison of ARMv8-A cores

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This is a table of 64/32-bit ARMv8-A architecture cores comparing microarchitectures which implement the AArch64 instruction set and mandatory or optional extensions of it. Most chips support 32-bit AArch32 for legacy applications, while the Falkor data center chip does not. All chips of this type have a floating-point unit (FPU) that is better than the one in older ARMv7 and NEON (SIMD) chips. Some of these chips have coprocessors, such as the AppliedMicro Helix that also includes cores from the older 32-bit architecture (ARMv7). Some of the chips are SoCs and can combine both ARM Cortex-A53 and ARM Cortex-A57, such as the Samsung Exynos 7 Octa.

Table

This list is incomplete; you can help by expanding it.
Company Core Released Revision Decode Pipeline
depth		 Out-of-order
execution		 Branch
prediction		 big.LITTLE role Execution
ports		 Fab
(in nm)		 Simultaneous multithreading L0 cache L1 cache
Instr + Data
(in KiB)		 L2 cache L3 cache Core
configu-
rations		 DMIPS/
MHz
ARM Holdings Cortex-A32 (32-bit)[1] 2017 ARMv8.0-A
(only 32-bit)		 ? No LITTLE ? 28[2] No No 8–32 + 8–32 0–1 MiB No 1-4+
Cortex-A35[3] 2017 ARMv8.0-A 2-wide[4] 8 No Yes LITTLE ? 28 / 16 / 14 / 10 No No 8–64 + 8–64 0 / 128 KiB–1 MiB No 1–4+ 1.78
Cortex-A53[5] 2014 ARMv8.0-A 2-wide 8 No Conditional+
Indirect branch
prediction		 big/LITTLE 2 28 / 20 / 16 / 14 / 10 No No 8–64 + 8–64 128 KiB–2 MiB No 1–4+ 2.24
Cortex-A55[6] 2017 ARMv8.2-A 2-wide 8 No big/LITTLE 2 28 / 20 / 16 / 14 / 10 No No 16–64 + 16–64 0–256 KiB/core 0–4 MiB 1–8+ ?
Cortex-A57[7] 2013 ARMv8.0-A 3-wide 15 Yes
3-wide dispatch		 Two-level big 8 28 / 20 / 16[8] / 14 No No 48 + 32 0.5–2 MiB No 1–4+ 4.6
Cortex-A65AE[9] 2019 ARMv8.2-A ? ? Yes Two-level ? 2 ? SMT2 No 16-64 + 16-64 64-256 KiB 0-4 MB 1–8 ?
Cortex-A72[10] 2015 ARMv8.0-A 3-wide 15 Yes
5-wide dispatch		 Two-level big 8 28 / 16 No No 48 + 32 0.5–4 MiB No 1–4+ 4.72
Cortex-A73[11] 2016 ARMv8.0-A 2-wide 11–12 Yes
4-wide dispatch		 Two-level big 7 28 / 16 / 10 No No 64 + 32/64 1–8 MiB No 1–4+ ~6.35
Cortex-A75[6] 2017 ARMv8.2-A 3-wide 11–13 Yes
6-wide dispatch		 Two-level big 8? 28 / 16 / 10 No No 64 + 64 256–512 KiB/core 0–4 MiB 1–8+ ?
Cortex-A76[12] 2018 ARMv8.2-A 4-wide 11–13 Yes
8-wide dispatch		 Two-level big 8 10 / 7 No No 64 + 64 256–512 KiB/core 1–4 MiB 1–4 ?
Cortex-A77[13] 2019 ARMv8.2-A 4-wide 11–13 Yes
10-wide dispatch		 Two-level big 12 7 No 1.5K entries 64 + 64 256–512 KiB/core 1–4 MiB 1-4 ?
Apple Inc. Cyclone[14] 2013 ARMv8.0-A 6-wide[15] 16[15] Yes[15] Yes No 9[15] 28[16] No No 64 + 64[15] 1 MiB[15] 4 MiB[15] 2[17] ?
Typhoon 2014 ARMv8.0‑A 6-wide[18] 16[18] Yes[18] Yes No 9 20 No No 64 + 64[15] 1 MiB[18] 4 MiB[15] 2, 3 (A8X) ?
Twister 2015 ARMv8.0‑A 6-wide[18] 16[18] Yes[18] Yes No 9 16 / 14 No No 64 + 64[18] 3 MiB[18] 4 MiB[18] 2 ?
Hurricane 2016 ARMv8.1‑A 7-wide[19] 16 Yes Yes "big" (In A10/A10X paired with "LITTLE" Zephyr
cores)		 9 16 (A10)
10 (A10X)		 No No 64 + 64[20] 3 MiB[20] (A10)
8 MiB (A10X)		 4 MiB[20] (A10)
No (A10X)		 2 + 2× Zephyr (A10)
3 + 3x Zephyr (A10X)		 ?
Zephyr 2016 ARMv8.1‑A 3-wide 12 Yes Yes LITTLE 5 16 (A10)
10 (A10X)		 No No 32 + 32[21] 1 MiB 4 MiB[20] (A10)
No (A10X)		 2 + 2× Zephyr (A10)
3 + 3x Zephyr (A10X		 ?
Monsoon 2017 ARMv8.2‑A[22] 7-wide 16 Yes Yes "big" (In Apple A11 paired with "LITTLE" Mistral
cores)		 13 10 No No 64 + 64[21] 8 MiB No 2x Monsoon + 4× Mistral ?
Mistral 2017 ARMv8.2‑A[22] 3-wide 12 Yes Yes LITTLE 5 10 No No 32 + 32[21] 1 MiB No 2x Monsoon + 4× Mistral ?
Vortex 2018 ARMv8.3‑A[23] 7-wide 16 Yes Yes "big" (In Apple A12 paired with "LITTLE" Tempest
cores)		 13 7 No No 128 + 128[21] 8 MiB No 2x Vortex + 4x Tempest ?
Tempest 2018 ARMv8.3‑A[23] 3-wide 12 Yes Yes LITTLE 5 7 No No 32 + 32[21] 2 MiB No 2x Vortex + 4x Tempest ?
Nvidia Denver[24][25] 2014 ARMv8‑A 2-wide hardware
decoder, up to
7-wide variable-
length VLIW
micro-ops		 13 Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW.		 Direct+
Indirect branch
prediction		 No 7 28 No No 128 + 64 2 MiB No 2 ?
Denver 2[26] 2016 ARMv8‑A ? 13 Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW.		 Direct+
Indirect branch
prediction		 "Super" Nvidia's own implementation ? 16 No No 128 + 64 2 MiB No 2 ?
Carmel 2018 ARMv8.2‑A ? Direct+
Indirect branch
prediction		 ? 12 No No 128 + 64 2 MiB (4 MiB @ 8 cores) 2 (+ 8) ?
Cavium ThunderX[27][28] ARMv8-A 2-wide ? No Two-level ? 28 No No 78 + 32[29][30] 16 MiB[29][30] No 8–16, 24–48 ?
ThunderX2
[31](ex. Broadcom Vulcan[32])		 May 2018[33] ARMv8.1-A
[34]		 4-wide
"4 μops"[35][36]		 ? Yes[37] Multi-level ? ? 16[38] SMT4 No 32 + 32
(data 8-way)		 256KB
per core[39]		 1MB
per core[39]		 16-32[39] ?
AppliedMicro Helix ? ? ? ? ? ? ? ? 40 / 28 No No 32 + 32 (per core;
write-through
w/parity)[40]		 256 KiB shared
per core pair (with ECC)		 1 MiB/core 2, 4, 8 ?
X-Gene ? 4-wide 15 Yes ? ? ? 40[41] No No 8 MiB 8 4.2
X-Gene 2 ? 4-wide 15 Yes ? ? ? 28[42] No No 8 MiB 8 4.2
X-Gene 3[42] ? ? ? ? ? ? ? 16 No No ? ? 32 MiB 32 ?
Qualcomm Kryo 2016 ARMv8-A ? ? Yes Two-level? "big" or "LITTLE"
Qualcomm's own similar implementation		 ? 14[43] No No 32+24[44] 0.5–1 MiB 2, 4 6.3
Kryo 2XX 2017 ARMv8-A 2-wide 11–12 Yes
7-wide dispatch		 Two-level big 7 10 LPE[45] No No 64 + 32/64? 512 KiB/Gold Core No 4 ?
2-wide 8 No Conditional+
Indirect branch
prediction		 2 No No 8–64? + 8–64? 256 KiB/Silver Core 4 ?
Kryo 3XX 2018 ARMv8.2-A 3-wide 11–13 Yes
8-wide dispatch		 Two-level big 8 10 LPP[45] No No 64+64[45] 256 KiB/Gold Core 2 MiB 4 ?
2-wide 8 No Conditional+
Indirect branch
prediction		 28 No No 16–64? + 16–64? 128 KiB/Silver 4 ?
Kryo 4XX 2019 ARMv8.2-A 4-wide 11–13 Yes
8-wide dispatch		 Yes big 8 N7 FF No No 64 + 64 512 KiB/Gold Prime

256 KiB/Gold

 2 MiB 1+3 ?
2-wide 8 No Conditional+
Indirect branch
prediction		 2 No No 16–64? + 16–64? 128 KiB/Silver 4 ?
Falkor[46][47] 11-8-2017[48] "ARMv8.1-A features";[47] AArch64 only (not 32-bit)[47] 4-wide 10–15 Yes
8-wide dispatch		 Yes ? 8 10 No 24 KiB 88[47] + 32 500KiB 1.25MiB 40-48 ?
Samsung M1/M2[49][50] 2015 ARMv8-A 4-wide 13[51] Yes
9-wide dispatch[52]		 Two-level big 8 14 / 10 No No 64 + 32 2 MiB[53] no 4 ?
M3[51][54] 2018 ARMv8.2-A 6-wide 15 Yes
12-wide dispatch		 Two-level big 12 10 No No 64 + 64 512 KiB per core 4096KB 4 ?
M4[55] 2019 ARMv8.2-A 6-wide 15 Yes
12-wide dispatch		 Two-level big 12 8 No No 64 + 64 512 KiB per core 4096KB 2 ?
Company Core Released Revision Decode Pipeline
depth		 Out-of-order
execution		 Branch
prediction		 big.LITTLE role Execution
ports		 Fab
(in nm)		 Simultaneous multithreading L0 cache L1 cache
Instr + Data
(in KiB)		 L2 cache L3 cache Core
configu-
rations		 DMIPS/
MHz

As Dhrystone (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads – use with caution.

See also

References

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